`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////
////                                                              //// 
////                                                              //// 
////  Part of the project chess controller                        ////  
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////  Description                                                 //// 
////   -                                 //// 
////                                                              //// 
////  To Do:                                                      //// 
////   -                                //// 
////                                                              //// 
////  Author(s):                                                  //// 
////      - Sergio Gonzalez Q, sergiogq@hotmail.es                ////
////      - Alejandro Morales A, ale3191@gmail.com                //// 
////                                                              //// 
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//FreqDivider
//El divisor es necesario para poder contabilizar el tiempo en segundos 

//Definicion del Modulo
module SystemClockDivider(
       input _clk_i,
		 input _rst_i,
		 output reg divided_freq_o
		 );

	
//Registro del contador utilizado para acumular tiempo en la seal con frecuencia de 250 Hz	
	reg [17:0] counter; //es de 18 bits para poder contar hasta 200000 (50MHz/250 = 20000) //0-17   //22

//Definicion del comportamiento del divisor

always @(posedge _clk_i) //en el flanco positivo del reloj
	begin
	if(_rst_i) // Si se presiona reset entonces 
		begin
		   counter<=0; // comienza a contar desde 0
		   divided_freq_o <= 0; // Mantiene la salida en 0
		end
	else
		if ( divided_freq_o == 1) // Si la salida es 1
			  divided_freq_o  <= ~  divided_freq_o ; // la niega
		else if(counter == 199999) // Si ya cont   //es 199999    //6249999
			begin
			   counter <= 0; //establece contador en 0
			   divided_freq_o <= ~ divided_freq_o; //niega la salida
			end //Se cuenta hasta 20000
		else
			counter <= counter + 1; // mientras no se alcance el valor se contina contando
	end

endmodule

